Ultra large scale integration (ULSI) has been achieved through high performance and high integration of semiconductor devices. In the ULSI, the minimum line width has a submicron size, and multi-layer wirings should be interconnected. When wirings having a very small line width are formed in multiple layers, it may be difficult to ensure a lithography margin in the upper layer. Thus, it is necessary to globally planarize each layer to ensure the lithography margin. To this end, a chemical mechanical polishing (CMP) process has been developed.
However, even when applying the CMP process, it is difficult to achieve overall planarization over the entire area of a semiconductor device. In particular, the semiconductor device includes a cell array area and a peripheral circuit area adjacent to the cell array area. Typically, the cell array area has a pattern density higher than that of the peripheral circuit area. In this case, during the CMP process, the cell array area is over-polished due to high polishing rate, the peripheral circuit area is under-polished due to low polishing rate, and thus the planarization cannot be achieved over the entire area. In this case, an error may occur during operation of the device.